I don't really know enough to refute it, but this seems deeply and bizarrely wrong. It doesn't account for transistor count or density just the size of the entire chip? With pipelining I don't think a signal has to travel across the entire chip every cycle. It also doesn't really address the question above, since single core CPU speeds haven't increased in 15 years even though transistors have kept getting smaller and closer together.
Seems like an intriguing napkin math limit/simplification though, I'd be interested if anyone could elaborate on if there's any substance to it.
The speed of EM signal in copper is roughly 60% of the speed of light. You also have to account for timing jitter and wait until you are sure that everybody has the signal to prevent going out of sync.
This means that reliable distance from a single clock is just a fraction of what the speed of signal theoretically allows.
Clock distribution networks use local clocks to buffer and amplify the global clock but they take a significant amount of chip area and make the chip larger. Clock distribution circuitry draws a significant amount of power. It can be 30-40% of the power usage. You want to use them as little as possible.
It is not wrong, it is rather correct. Speed of propagation in semiconductor materials is at most a third of speed of light in vacuum. So the distance travelled is rather limited for a signal. Also, a signal might have to traverse a few transistors or gates, so frequency in the 3GHz range does really limit processor sizes to the order of millimeters. You already said how to get around it: Pipelines, that limits the area a signal has to propagate. Also, one has to take care to make signals arrive early enough in the longest possible signal path as well as to distribute the clock in a way for it to arrive at aligned times everywhere, so you need a clock distribution net with known delays, etc. Chip timing is black art.
When designing chips or doing layout for FPGA designs, we do something called timing analysis to find out if signals get to where they should do such that the chip is stable ("meets timing").
There is a lot more to it than just distance. The transistors have speeds, to start with.
That and just because this size gives a bound on how quickly you can do things, the transistor count is also increasing, so the actual clock doesn't increase all that much.
Seems like an intriguing napkin math limit/simplification though, I'd be interested if anyone could elaborate on if there's any substance to it.